1. Field of the Invention
The present invention relates to a geometry processor for three-dimensional (3D) graphics of SIMD (Single-Instruction stream and Multiple-Data stream) type and, more specifically, to a geometry processor for 3D graphics capable of performing input/output to and from peripherals in parallel with geometry calculation.
2. Description of the Background Art
Recently, widening range of objects of image processing has developed a demand for systems requiring 3D graphics processing. It is often the case that such systems require real time processing.
It is noted that image processing, especially 3D graphics processing has the following features.
(1) Frequent conditional branching
(2) Computation of inverse (1/x), square root ({square root over (x)}), inversed square root (1/{square root over (x)}), x raised to the ath power (a representing floating point data)
(3) Calculation of product and summation (c=axc3x97b+c)
Such calculations require formidable amount of computation. For this reason, there has not been any geometry processor having such an architecture that is capable of processing all these calculations at high speed. Accordingly, in the conventional system involving image processing, the time of processing has been made long because of the slow speed of calculation of the 3D graphics processing.
Therefore, an object of the present invention is to provide a geometry processor capable of processing geometry calculations at high speed, and to provide a floating point power computing apparatus and a data output control apparatus used in the processor.
Another object of the present invention is to provide a geometry processor capable of processing geometry calculation at high speed and in addition, capable of data input/output to and from peripherals at high speed, and to provide a floating point power computing apparatus and a data output control apparatus, used in the processor.
Another object of the present invention is to provide a geometry processor capable of processing calculations frequently encountered in geometry calculations to enable high speed processing of geometry calculations and in addition, capable of input/output of data to and from peripherals at high speed, and to provide a floating point power computing apparatus and a data output control apparatus used in the processor.
A still further object of the present invention is to provide a geometry processor capable of geometry calculations and data input/output to and from peripherals at high speed, and in addition, capable of executing data input/output and geometry calculations in parallel, as well as to provide a floating point power computing apparatus and a data output control apparatus used in the processor.
The geometry processor in accordance with the present invention includes: first and second external interface ports independent from each other, connected to a host processor and a rendering processor (Rendering Controller: RC), respectively; and a geometry calculation core for processing geometry calculation applied through the first external interface from the host processor. The geometry calculation core includes: a plurality of SIMD type floating point calculating units; a floating point power computing unit; an integer calculating unit; a controller for processing data from the host processor by controlling the plurality of floating point calculating units, floating point power computing unit and the integer calculating unit, in response to an instruction from the host processor; and an output controller for outputting the processed data to the rendering processor through the second external interface.
In the geometry processor in accordance with the present invention, the geometry calculation core includes the floating point calculating unit employing the SIMD type architecture, and further employs the floating point power computing unit and the integer calculating unit. This allows high speed processing of geometry calculation especially in the 3D graphic system. Further, as the geometry processor has three external interfaces, data output after calculation and operation of the geometry calculation core can be executed in parallel.
Preferably, the geometry calculation core further includes: a first data bus capable of communication with the first and second external interface ports, the plurality of floating point calculating units, the floating point power computing unit, the integer calculating unit and the controller; a second data bus connecting the plurality of floating point calculating units and the floating point power computing unit; a third data bus for applying data received from the plurality of floating point calculating units and the floating point power computing unit to the second external interface port; and first, second and third address buses capable of communicating with the first external interface port, the plurality of floating point calculating units, the geometry processor, the integer calculating unit and the controller, for carrying three addresses generated by the controller. The first data bus is capable of data multicasting among components connected to the first data bus.
Data necessary for calculating process can all be prepared in one cycle, and at the same time, results of calculating process can be stored in the destinations. Accordingly, pipeline processing can be implemented easily, and the speed of processing is improved.
More preferably, the second data bus includes a first uni-directional data bus for applying outputs of the plurality of floating point calculating units to the geometry processor, and a second uni-directional data bus for applying an output of the geometry processor to the plurality of floating point calculating units.
As two data buses are used for data exchange within the geometry calculation core, the wait time until the data bus is granted is eliminated, resulting in faster processing.
More preferably, the geometry processor further includes an output FIFO (First-In First-Out buffer) provided between the third data bus and the second external interface. The third data bus has a function of converting parallel data as the outputs of geometry processor for 3D graphics and the geometry processor to serial data and to apply the resulting data to the output FIFO. The data output accompanied with serial data conversion to the output FIFO is executed parallel to and independent from the processing in the geometry calculation core. This enables multiplexing of processings, further improving the speed of operation.
In another configuration, the controller of the geometry processor includes: an instruction memory for storing a graphic processing instruction applied through the first external interface port; a sequencer decoding an instruction stored in the instruction memory and controlling operation sequences of the plurality of floating point calculating units, the geometry processor and the integer calculating unit in accordance with the result of decoding; and an address generating circuit which generates three addresses to be output to the first, second and third address buses under the control of the sequencer.
The sequencers of calculations are controlled by a controller separate from the host processor, and three addresses for executing calculations are generated and output to three address buses. Therefore, execution cycle of calculation can be made short, and the overall processing speed is improved.
According to another aspect of the present invention, the geometry processor includes: an external interface port connected to a host processor and including a first register storing information to be exchanged with the host processor; a geometry calculation core for processing an instruction applied from the host processor through the external interface; a second register; and a circuit for copying contents of the first register applied from the host processor to the second register. The geometry calculation core operates in accordance with the contents of the second register. The geometry processor further includes a circuit for performing communication with the host processor and the external interface port, parallel to the operation of the geometry calculation core in accordance with the contents of the second register.
After the contents of the first register are copied to the second register, it becomes possible to perform the operation of the geometry calculation core based on the contents of the second register and the processing of storing the second instruction to the first register. This allows multiplexing of processings, improving speed of operation.
More preferably, the geometry processor further includes an input FIFO for storing data applied from the host processor to the geometry calculation core. The geometry calculation core accesses the input FIFO and if the input FIFO is empty, it temporarily stops its operation.
According to a still further aspect of the present invention, the floating point power computing apparatus includes a look-up table including a logarithmic table having a prescribed number (for example, 2) as a base for certain numbers and a power table having the aforementioned prescribed number as a base for certain numbers, for receiving an input of a certain number and outputting the corresponding logarithmic or a corresponding power; and a calculating circuit receiving inputs of a first number represented by first floating point data and a second number n, for computing, with reference to the look-up table, the first number raised to the nth power.
The power can be calculated by a simple structure and the process of calculation can be implemented in pipelines. Therefore, graphics processing involving frequent power calculations can be done at a higher speed.
According to another aspect of the present invention, the data output control apparatus includes: a data bus connected to a plurality of calculation processing units each having a prescribed memory for storing result of calculating process and receiving data from the prescribed memory; an output FIFO including a plurality of output FIFO banks each having a storing section and an address section for the storing section; and a burst transfer control connected between the data bus and the output FIFO, responsive to an address signal and a data output request applied from the calculation processing unit through the data bus, which reads data from the prescribed memory and transfers burst of the data to a position determined by the address signal of that one of the plurality of output FIFO banks which is determined by the data output request.
In response to the output request from the calculation processing unit, data transfer to the output FIFO is performed in burst, and therefore output processing itself can be done at high speed. Further, in this period, it is possible for the calculation processing unit to execute the next calculating process parallel to the data output, and therefore the overall processing speed can further be improved.
Preferably, the burst transfer controller includes: a circuit receiving the number of data to be transferred from the calculation processing unit which has output the data output request, counting the number of data blocks to be burst-transferred and detecting termination of transfer; a circuit which generates and applies to the output FIFO a write pointer of the output FIFO based on the address signal; and a circuit responsive to a signal indicating whether writing is possible or not applied from the output FIFO which controls continuation and stopping of data transfer to the output FIFO.
Even when reception of data is not possible because of data left in the output FIFO, data output can be controlled without the necessity of control by the host processor or the calculation processing unit. Therefore, the load on the calculation processing unit for ensuring normal output processing is not increased.